1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to high performance microelectronic flash memory cells and to the art of manufacturing high performance microelectronic flash memory cells. Even more specifically, this invention relates to high performance microelectronic flash memory cells with reduced source resistance and improved short channel effect in deep sub-0.18 μm flash memory technology.
2. Discussion of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory array are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells in either a column or a row are connected together and each column or row common source connections are then connected to a common source voltage Vss. This arrangement is known as a NOR flash memory configuration.
A cell is programmed by applying a voltage, typically 9 volts to the control gate, applying a voltage of approximately 5 volts to the drain and grounding the common voltage source Vss, which causes hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative change therein which increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying typically 5 volts to the control gate, applying 1 volt to the bitline to which the drain is connected, grounding the common source voltage Vss, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, a cell is erased by applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. A cell can also be erased by applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float. Another method of erasing is by applying 5V to the P-well and minus 10V to the control gate while allowing the source/drain to float.
However, as the dimensions of the flash memory array have been aggressively scaled down and the product arrays produced with ultra high density, the greatest challenge for deep sub-0.18μm high performance non-volatile memory cell design is to control the short channel dimension in order to control the short channel effects, such as Vt, rolloff, high DIBL and excess column leakage, accompanied with less tolerance of the polysilicon gate length variation across the product array.
Therefore, what is needed is a method of providing a lightly doped source junction near the critical gate region and a heavily doped source junction away from the critical gate region in such a way that the lateral diffusion is decreased while maintaining a low Vss resistance.